1. Field of the Invention
This invention relates generally to Integrated Circuits and, in particular, to routing wires within a programmable logic device (PLD).
2. Description of the Related Art
The basic building block of the PLD is a logic element that is capable of performing limited logic functions on a number of input variables. The logic element is typically equipped with circuitry to programmably implement the “sum of products” logic, as well as one or more registers to implement sequential logic. Conventional PLDs combine together large numbers of such logic elements through an array of programmable interconnections to facilitate implementation of complex logic functions. PLDs have found particularly wide application as a result of their combined low up-front cost and versatility to the user.
A variety of PLD architectural approaches arranging the interconnect array and logic elements have been developed to optimize logic density and signal routability between the various logic elements. The logic elements are arranged in groups of, for example, eight to form a larger logic array block (LAB). Multiple LABs are arranged in their two-dimensional array and are programmably connectable to each other through global horizontal and vertical interconnect channels. Each of the horizontal and vertical interconnect channels include one or more routing wires. Signals that are routed to and from the logic regions over vertical and horizontal conductors form signal paths. Particular circuitry, including, for example, pass gates, multiplexors, and drivers may be used to couple and drive signals onto horizontal or vertical wires, or to receive signals from the horizontal or vertical wires and drive them to the logic regions. Circuitry-forming connections between horizontal wires, vertical wires, and logic regions may be programmable. One example of a programmable connection is a pass gate coupled through a random access memory bit circuit where the pass gate programmably connects a vertical wire to an input multiplexor of the logic region. Other examples may include connections based upon static or dynamic random access memory, electrically erasable read-only memory, flash, fuse and anti-fuse programmable connections.
FIG. 1 is a simplified schematic diagram illustrating the implementation of an H4 segmented wiring scheme on a right edge of a chip. As can be seen, at the right edge of the chip, because of the regular pattern defined by the H4 segmented wiring scheme, undriven wires 100 result. It should be appreciated that undriven wires 100 would have been associated with a driver had there been any logic blocks to the right of Input/Output (IO) block 102. Similarly, some of the wires that drive towards the right edge of the chip are relatively short because of the truncation effects due to the proximity to the edge of the chip. For example, wires 104 are associated with either one or two LAB blocks because of the edge effects. It should be appreciated that similar effects occur at the left and vertical edges of the chip, as well as any core intrusion in the chip such as large random access memory, microprocessors, and the phase lock loop (PLL) block. Wires 104 are associated with drivers that are configured to drive signals to 4 LABs. However, due to the short length of the wires the driver/wire configuration can only communicate with three or fewer LABs, or a single I/O block.
As a result, there is a need to solve the problems of the prior art to more efficiently utilize the signal driving capacity of the underutilized drivers at the edge of a chip having a segmented routing scheme.